Chris Spear’s OpenVera / Vera Examples
OpenVera is a HVL - hardware verification language. It was originally developed by Sun under the name Vera and implemented by System Science. OpenVera is based on Verilog, C++, and Java, with addtional constructs specifically for verification. It is easy to learn and use, and allows [...]

FPGAs are fun!

Yesterday I recieved “Hacking the Xbox: An Introduction to Reverse Engineering” from BookPool ( 50 cents less than amazon.com’s price ) and finished reading in one sitting. This is the best technical book I have ever read. Wow! an amaging story annotated with political, social issues facing today’s hacker and impact of [...]

Asic-world Verilog Page

LOGIC SYNTHESIS OF VLSI CIRCUITS stanford class site

ASIC Standard Cell Library Design by Graham Petley
This site contains support material for the book, The Art of Standard Cell Library Design.

UCSD VLSI CAD Laboratory

Synthesis Tools (sofware …) List

CAD of VLSI Systems

Dr. Lim’s Lecture Notes